Generally, a memory system using a DDR (Double Data Rate) 3 memory or the like includes a memory controller which works as a transmitting element, a plurality of memory devices which work as receiving elements, and a printed wiring board including signal-connecting wires for mounting the memory controller and the memory devices thereon.
The memory controller transmits an address command signal, a plurality of the memory devices are controlled by receiving the address command signal, and the memory controller and a plurality of the memory devices transmit and receive a data signal to and from each other. In particular, a plurality of DDR3 memories are mounted on and used for electronic equipment having high functions in many cases, in order to secure its memory capacity.
The DDR3 memory has a function of adjusting the timing of transmitting a signal integrated therein. A plurality of the memory devices are connected by a wiring structure in which a plurality of branch wires are sequentially branched from one main wire, which is referred to as fly-by that can increase a speed of an address command signal (see NPL 1).
FIG. 13 is a wiring diagram illustrating a wiring configuration according to a conventional fly-by method. A memory controller 200 is connected to wires to which a termination potential is applied through a termination resistor, through a plurality of main wires. In FIG. 13, two main wires 11 and 12 are illustrated among the plurality of the main wires. Respective memory devices 3001 to 3004 are connected to the main wire 11 through branch wires 31 to 34 which are branched at branch points P1 to P4, respectively. In addition, the respective memory devices 3001 to 3004 are connected to the main wire 12 through branch wires 41 to 44 which are branched at branch points P5 to P8, respectively. Terminations of the main wires 11 and 12 are connected to a termination wire 403 to which termination voltage is applied, through termination resistors 401 and 402.
FIGS. 14A and 14B are sectional views illustrating the wiring structure in the conventional printed wiring board. As is illustrated in FIG. 14A and FIG. 14B, two layers of inner layers of a printed wiring board are used for the main wires 11 and 12 which are address command wires of the DDR3 memories.
Specifically, as is illustrated in FIG. 14A, the main wire 11 uses an inner layer 13, and as is illustrated in FIG. 14A, the main wire 12 uses an inner layer 14. A BGA (Ball Grid Array) type of semiconductor package is used for the memory devices 3001 to 3004. Each of the branch wires 31 to 34 formed on the printed wiring board includes a via which is electrically connected to the main wire 11, a mounting pad which is connected to the receiving terminal of the semiconductor package, and a leading wire which connects the via with the mounting pad. Similarly, each of the branch wires 41 to 44 includes a via which is electrically connected to the main wire 12, a mounting pad which is connected to the receiving terminal of the semiconductor package, and a leading wire which connects the via with the mounting pad.
In the case of the wiring structure in which a plurality of branch wires are sequentially branched from one main wire, which is referred to as the fly-by, as the length of the branch wire increases, the decay and reflection of the signal increase, which causes the turbulence of the waveform of the signal that reaches memory devices 3001 to 3004. Accordingly, ringing increases in the branch wires 41 to 44, and especially in the branch wire 41 which is branched from the branch point P5 that is nearest to the starting end of the main wire 12, because the wiring length is longer than those of the branch wires 31 to 34, and there is the case where conditions on input voltage for a signal cannot be satisfied. Accordingly, it is important to shorten the branch wire, in order to satisfy the conditions on the input voltage for a signal.
In recent years, the number of the signal wires for transmitting the signal to the memory device therethrough has extremely increased. Because of this, when the branch wires are formed according to the fly-by mode, the position of the via cannot but become far from the signal terminal of the memory device, and cannot but become nonuniform, in order to secure the region which forms the via.